(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming field isolation.
(2) Description of prior art and background to the invention.
The formation of integrated circuit devices on silicon substrates requires that a means be provided to electrically isolate the various circuit components from each other. In many cases pin junctions themselves can be used to form at least part of the necessary isolation. Most isolation requirements, which cannot be resolved by circuit design, relate to the lateral isolation of devices. To some extent, junction isolation can be used here also. However, as device technology leads to smaller and smaller geometries as well as shallower structures, junction isolation technology becomes very limited.
The successful use of silicon for integrated circuits for the last thirty years can, in part, be attributed to the marvelous insulating properties of it's oxide. No other commonly known semiconductor material has this unique feature. Thus silicon oxide has become well established as the isolation material for integrated circuit chips. Earliest usage of this material involved growing it on the substrate in selected regions which are defined by an oxidation masking material. To this end, silicon nitride has come into widespread use. Referring to FIG. 1, a pad silicon oxide film 12 several hundred Angstroms thick, is grown on the surface of a silicon wafer 10. Next a silicon nitride layer 14 is deposited to a thickness of several thousand Angstroms using a chemical-vapor-deposition (CVD) process. be silicon nitride layer 14 is patterned and used as a hard mask for the isolation oxidation. The pad oxide 12 serves as a buffer layer, preventing the highly stressed silicon nitride from causing dislocations in the silicon.
Using standard photolithographic techniques followed by plasma etching or reactive ion etching (RIE), a pattern is defined in the silicon nitride, exposing regions which are to become the isolation regions. Referring next to FIG. 2, the wafer 10 is subjected to an oxidizing ambient at elevated temperatures, during which the exposed areas are converted to silicon oxide 16. The oxidation The oxidation proceeds at the oxide-silicon interface. Thereby pockets of silicon oxide 16 several thousand Angstroms deep can be formed in the patterned areas. These pockets 16 provide the necessary electrical isolation for the subsequently formed semiconductor devices. The process just described has become known by several names, one of which is LOCOS an acronym for LOCal Oxidation of silicon. LOCOS has been practiced for over twenty-five years and has successfully been developed to keep the pace with shrinking device dimensions.
One of the problems which becomes serious as device geometries shrink to dimensional levels below half micron, is the ability of the silicon nitride mask to faithfully replicate the photoresist pattern after it has been etched. This is true of any hardmask. In a conventional etching process the photoresist mask suffers some deterioration by isotropic etching during the patterning etch, particularly during plasma etching. As the mask deteriorates, the walls of the subjacent silicon nitride openings develop a taper so that the dimensions at the base of the silicon nitride pattern are not the same as those of the photomask. This is illustrated by FIGS. 3A and 3B. In FIG. 3A there is shown a cross section of a wafer 10 a pad oxide layer 12 and a silicon nitride layer 14. A photoresist layer 16 is patterned to provide the features 20 and 22 which protect regions of the wafer wherein active device areas are to be formed. The taper angle .alpha..sub.1 in a typical example is about 85.degree.. The dimension "a.sub.1 " determines the width of the active area and the dimension "b.sub.1 " determines the width of the oxide isolation.
FIG. 3B shows the same cross section after the silicon nitride hard mask has been patterned by plasma etching. The dashed lines represent the original profile shown in FIG. 3A. Because of deterioration of the photomask 20, the dimension "a.sub.2 " at the base of the silicon nitride hard mask feature becomes somewhat smaller than "a.sub.1 ". Similarly the dimension "b.sub.2 " for the isolation region width becomes somewhat larger than the corresponding photomask dimension "b.sub.1 ". The angle a also exhibits a small decrease after the silicon nitride is etched.
When these dimensions are sufficiently large compared to the resolution of the photolithographic equipment, the standard practice is to design the photomask with a bias. That is to say the dimensions of the photomask are adjusted so that the proper design dimension is realized in the silicon nitride hard mask. Additional bias is also incorporated to compensate for the small amount of oxide which grows under the edge of the silicon nitride, commonly referred to as "birds beak", during the subsequent isolation oxidation.
When the dimensions of the photomask approach the limits of resolution of the photolithography, however, the inclusion of a mask bias is best avoided. It thus becomes desirable to reduce the amount of deterioration of the photomask during the patterning etch, in order to minimize the required photomask bias. The current invention provides a method for improving the photomask so that the silicon nitride hard mask properly replicates the dimensions of the photomask and the need for a design bias is eliminated. This accomplished by eliminating the isotropic lateral etching of the photomask.
Tam et. al, U.S. Pat. No. 4,613,400 cites a method for increasing the etch resistance of a photoresist mask used for the etching of silicon. By employing a plasma by containing HCl and BCl.sub.3 in the presence of silicon or silicon containing materials, a spongy coat is formed over the photoresist. This sponge-like coat is then oxidized by subjecting it to an atmosphere containing HCl and oxygen to form a an inorganic cap which is resistant to a subsequent silicon etchant.
Giammarco et. al. U.S. Pat. No. 4,707,218 reduce pattern dimensions of a photoresist mask by depositing a conformal layer of a material over the patterned mask and then performing an anisotropic etch forming sidewalls within the mask pattern. This procedure was proposed to form openings smaller than the capability of the lithography. This method, which has the disadvantage of additional processing steps and deposited films, is not a viable alternative to photomask biasing, particularly in sub-half micron technology.
Kadomura, U.S. Pat. No. 5,342,481 deposit material in a microwave plasma along the edges of a negatively tapered resist mask in order to remove the taper and provide a substantially vertical sidewall. This mask is then used to etch layers which require radical mode etching such as polysilicon or aluminum. Removal of the photomask taper permits these materials to be etch without dimensional changes. SiCl.sub.4 and N.sub.2 are used to form the material for filling in the taper. In another example S.sub.2 F.sub.2 and H.sub.2 S were used.